Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim

Farida Memon; Aamir Hussain Memon; Shahnawaz Talpur; Fayaz Ahmed Memon; Rafia Naz Memon

doi:10.22581/muet1982.1603.17

Farida Memon Department of Electronic Engineering, Mehran University of Engineering and Technology, Jamshoro.
Aamir Hussain Memon Institute of Information and Communication Technology, Allama II Kazi Campus, University of Sindh, Jamshoro
Shahnawaz Talpur Department of Computer Systems Engineering, Mehran University of Engineering and Technology, Jamshoro
Fayaz Ahmed Memon Department of Computer Systems Engineering, Quaid-e-Awam University of Engineering, Science and Technology, Nawabshah.
Rafia Naz Memon Department of Information Technology, Quaid-e-Awam University of Engineering, Science and Technology, Nawabshah

DOI: https://doi.org/10.22581/muet1982.1603.17

Keywords: Depth Estimation, Shape From Focus, Hardware Description Language Coder, Field Programmable Gate Arrays

Abstract

In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.