Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim

In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floatingpoint design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.

processing algorithms is associated with various limitations like processing speed and portability [1]. Real-time image processing is an emerging trend in the field of CV. FPGAs are often used as a hardware platform for implementing the algorithms. FPGAs have become a preferred choice due to their re-configurability, high performance and low power consumption [2]. Hardware implementation provides greater speed than software, but associated time lengthens the development of hardware design. FPGA implementations are often written in the HDLs using VHDL or Verilog, which take a very long implementation time.
Model based hardware design has become very popular in recent years. This design methodology provides a framework for the integration of different phases of the development process. It reduces the lead time to create a self-sufficient model. The design phases associated with the model based design allow the designer to locate and correct errors prior to system prototyping. Thus, model based design effectively serves as a tool for rapid prototyping, system validation and testing.  Nayar and Nakagawa [5] have developed the focus measure based on SML (Sum-of-Modified-Laplacian)

BACKGROUND OF DEPTH ESTIMATION
operator. Several focus operators are developed in [10,11] using the statistical analysis of image intensities.

DESIGN METHODOLOGY
A model based design using HDL Coder is proposed in order to develop hardware design of depth estimation on a FPGA platform. The proposed design is an alternative to traditional FPGA design flow using manual HDL coding which is tedious, error prone and highly time consuming.
The model based design flow of depth estimation algorithm using HDL Coder is shown in Fig. 1.
Methodology includes designing of depth estimation algorithm in MATLAB, generating VHDL code from MATLAB algorithm using HDL Coder and verification with co-simulation using ModelSim simulator.

MATLAB Algorithm Design
The MATLAB design of depth estimation algorithm is

MATLAB to VHDL Workflow
The overview of the MATLAB to VHDL generation workflow of depth estimation algorithm is given in Fig. 3.

Verify Floating-Point
The MATLAB floating-point model of design is simulated before the generation of VHDL code, to verify that it runs and offers a baseline to compare with the generated VHDL code. Coder executes the test bench of floating point model and shows all plots, variables and outputs of design. Errors in this model will propagate through all subsequent steps and present in the final bit stream.  Table 1.

Verify Fixed-Point
In

Generate RTL
After the verification of fixed-point model with the corresponding floating point design, Coder generates a RTL model from the fixed-point MATLAB code. In addition to generating VHDL code, a test-bench is also created to verify the generated code. Following files of the design are produced during this step as shown in Table 2.

RESULTS AND DISCUSSION
The A small selection of image frames and ground truth depth map is presented in Fig. 5(a-e). The depth map and focused image of a simulated cone is obtained by applying described depth estimation algorithm presented in Fig. 6(a-b). As compared with ground truth depth map given in Fig. 5 Fig. 9 and intensity values for an eight-bit image in Fig. 10.
Figs. 9-10 show the plots for reference design, cosimulation as well as the difference between the two.
From the plots it is clear that, both algorithms are similar.

CONCLUSION
The modern programmable devices in combination with appropriate software packages for synthesis and simulation give a significantly accelerated design process of electronic systems. Simulink HDL Coder is a simple and useful tool for developing and analyzing the algorithms. This approach for automatic generation of hardware descriptions models and systems saves significant amount of time for code writing, debugging and verification of the generated hardware. A novel frame work is developed which generates a hardware description in VHDL for a depth estimation algorithm from a MATLAB model, suitable to run on an FPGA. The generated hardware has been successively verified functionally by co-simulation using ModelSim software. Experimental results indicate that VHDL estimated depth map is comparable in accuracy to the full precision MATLAB's output and accurate depth is estimated using this method. Due to the drastic reduction of design time, this automatic method of converting an algorithm into a hardware design proved to be feasible. Future work includes implementation and evaluation of generated VHDL design on FPGA architecture.