Mehran University Research Journal Of Engineering &
Technology (HEC Recognized In Category "X")
Publishing Since 1982.



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Efficient Implementation of Ternary SDM Filters using State-of-the-Art FPGA

Keywords: Ternary FIR filter, FPGA, Sigma Delta Modulation, VHDL Implementation.

Mehran University Research Journal of Engineering & Technology

Volume 30 ,  Issue 2

Tayabuddin   Memon , Paul   Beckett , Amin  Z Sadik ,

References
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2. Thompson, A.C., Hussain, Z.M., and O'Shea, P., "Efficient Digital Single-Bit Resonator", IEEE Electronic Letters, Volume 40, pp. 1396-1397, 2004.
3. Thompson, A.C., Hussain, Z.M., and O'Shea, P., "Performance of a New Single-Bit Ternary Filtering System", Australian Telecommunications, Networks and Applications Conference, Melbourne, 2003.
4. Sadik, A.Z., Hussain, Z.M., and O'Shea, P., "An Adaptive Algorithm for Ternary Filtering", IEE Electronics Letters, Volume 42, pp. 420-420, March, 2006.
5. Rusu, A., Rodriguez de Llera Gonzalez, D., and Ismail, M., "Reconfigurable ADCs Enable Smart Radios for 4G Wireless Connectivity", IEEE Circuits and Devices Magazine, Volume 22, pp. 6-11, 2006.
6. Memon, T.D., Beckett, P., and Hussain, Z.M., "Design and Implementation of Ternary FIR Filter Using Sigma Delta Modulation", ISCCC'09, 2009.
7. Memon, T.D., Beckett, P., and Sadik, A.Z., "Performance-Area Tradeoffs in the Design of Short Word Length FIR Filter", 5th IEEE International Conference on MEMS, Nano and Smart Systems, Dubai, UAE, 2009.
8. Galton, I., "Delta-Sigma Data Conversion in Wireless Transceivers", IEEE Transaction on Microwave Theory and Techniques, Volume 50, pp. 302-315, January, 2002.
9. Chen, D., "VHDL Implementation of Fast Adder Tree", Department of Electrical Engineering, Linkoping University, 2005.