Ternary and Multi-Bit FIR Filter Area-Performance
Tradeoffs in FPGA
Keywords: Ternary, VHDL, FPGA, Sigma-Delta Modulation
Mehran University Research Journal of Engineering & Technology
Volume 32 , Issue 1
KHALIL-UR-RAHMAN DAYO , TAYAB DIN MEMON ,
References
| 1. |
|
| 2. |
Thompson, A.C., "Techniques in Single-Bit Digital
Filtering", Ph.D. Thesis, RMIT University, Melbourne,
2004. |
| 3. |
Sadik, A., Hussain, Z., and O'Shea, P., "Adaptive
Algorithm for Ternary Filtering", Electronics Letters,
Volume 42, pp. 420-421, 2006. |
| 4. |
Sadik, A.Z., and Hussain, Z.M., "Adaptive LMS Ternary
Filtering", IEEE Region 10 TENCON, Melbourne,
Australia, 2005. |
| |
|
|