Article Information  
Sigma Delta Modulation Based Ternary FIR Filter Mapping on FPGA

Keywords: Sigma Delta Modulation, FPGAs, Ternary FIR Filter, VHDL.

Mehran University Research Journal of Engineering & Technology

Volume 30 ,  Issue 3

Tayabuddin   Memon , Bhawani  Shankar  Chowdhry , Khalil-Ur-Rahman  Dayo ,

References
1. Memon, T.D., Beckett, P., and Sadik, A.Z., "Performance-Area Tradeoffs in the Design of Short Word Length FIR Filter", IEEE ICMENS, Dubai, UAE, pp. 67-71, 2009.
2. Galton, I., "Delta-Sigma Data Conversion in Wireless Transceivers", IEEE Transaction on Microwave Theory and Techniques, Volume 50, No. 1, Part-2, pp. 302- 315, 2002.
3. Memon, T.D., Beckett, P., and Hussain, Z.M., "Design and Implementation of Ternary FIR Filter Using Sigma Delta Modulation", ISCCC, pp. 169-174, 2009.
4. Sadik, A.Z., Hussain, Z.M., and O'Shea, P., "A Single-Bit Digital DC-Blocker Using Ternary Filtering", IEEE Tencon, Melbourne, Australia, 2005.
5. Sadik, A.Z., Hussain, Z.M., and O'Shea, P., "An Adaptive Algorithm for Ternary Filtering", IEE Electronics Letters, Volume 42, No. 7, pp. 420-420, 2006.
6. Thompson, A.C., Hussain, Z.M., and O'Shea, P., "A Single-Bit Narrow-band Bandpass Digital Filter", IEAUST Electronic Journal, 2005.
7. Thompson, A.C., O'Shea, P., Hussain, Z.M., and Steele, B.R., "Efficient Single-Bit Ternary Digital Filtering Using Sigma-Delta Modulator", IEEE Letters on Signal Processing, Volume 11, No. 2, pp. 164-166, 2004.
8. Thompson, A.C., Hussain, Z.M., and O'Shea, P., "Efficient Digital Single-Bit Resonator", IEEE Electronic Letters Volume 40, No. 22, pp. 1396-1397, 2004.
9. Dick, C., and Harris, F., "FPGA Signal Processing Using Sigma-Delta Modulation", IEEE Signal Processing Magazine, Volume 17, No. 1, pp. 20-35, 2000.
10. Sadik, A.Z., Hussain, Z.M., and O'Shea, P., "Structure for Single-Bit Digital Comb Filtering", APCC, pp. 545-548, Perth, Australia, 2005.
11. Benvenuto, N., Franks, L.E., and Jr, F.S.H., "Realization of Finite Impulse Response Filters Using Coefficients +1,0, and -1", IEEE Transactions on Communications, Volume COMM-33, No. 10, 1985.
12. Ng, C.W., Wong, N., and Ng, T.S., "Bit-Stream Adder and Multiplier for Tri-Level Sigma-Delta Modulators", IEEE Transaction on Circuits and Systems-II: Express Briefs, Volume 54, No. 12, pp. 1082-1086, 2007.
13. Macpherson, K.N., and Stewart, R.W., "Area Efficient FIR Filters for High Speed FPGA Implementation", IEE Proceedings of Image Signal Processing, Volume 153, No. 6, pp. 711-720, 2006.
14. Meher, P.K., Chandrasekaran, S., and Amira, A., "FPGA Realization of FIR Filter by Efficient and Flexible Systolization Using Distributed Arithmetic", IEEE Transaction on Signal Processing, Volume 56, No. 7, pp. 3009-3017, 2008.
15. Thompson, A.C., and Hussain, Z.M., "Performance of a Single-Bit Digital Non-Coherent Baseband BFSK Demodulator", WITSP, University of South Australia, Adelaide, 2004.
16. Pervez, A.M., Sorensen, H.V., and Spiegel, J.V.D., "An Overview of Sigma-Delta Converters", IEEE Signal Processing Magazine, pp. 61-84, 1996.
17. Sadik, A.Z., Hussain, Z.M., and O'Shea, P., "Structure for Single-Bit Digital Comb Filtering", IEEE Asia-Pacific Conference on Communication, pp. 545-548, Perth, Australia, 2005.
18. Chen, D., “VHDL Implementation of Fast Adder Tree”, Masters Thesis, Linkoping University, 2005.
19. Memon, T.D., Beckett, P., and Sadik, A.Z., “Effecient Implementation of Ternary SDM Filters Using Stateof- the-Art FPGA”, Mehran University Research Journal of Engineering & Technology, Volume 30, No. 2, pp. 207-212, Jamshoro, Pakistan, April, 2011.