Mehran University Research Journal Of Engineering &
Technology (HEC Recognized In Category "X")
Publishing Since 1982.



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Area Efficient S-Box Approach for SubByte Transformation in AES

Keywords: AES, S-BOX, FPGA, BRAM

Mehran University Research Journal of Engineering & Technology

Volume 29 ,  Issue 4

SALEHA  ZAKA , ARSHAD  AZIZ , DUR-E-SHAWAR  KUNDI ,

References
1. FIPS-197 “Advanced Encryption Standard FIPS 197”, NIST (National Institute of Standards and Technology), 2001 http://csrc.nist.gov/publications/ fips/fips197/fips- 197.pdf
2. Liu, B., and Baas, B.M., “Parallel AES Encryption Engines for Many-Core Processor Arrays”, IEEE Transactions on Computers, Volume 62, pp. 536-547, 2013
3. Luo, A.W., Yi, Q.M., and Shi, M., “Design and Amplementation of Area-Optimized AES based on FPGA”, International Conference on Business Management and Electronic Information, Volume 1, pp. 743-746, 2011
4. Aziz, A., and Ikram, N., “An Efficient FPGA Based Sequential Implementation of Advanced Encryption Standard”, ITI 3rd International Conference on Information and Communications Technology, Enabling Technologies for the New Knowledge Society, pp. 875-882, 2005
5. Standaert, F.X., Rouvroy, G., Quisquater, J.J., and Legat, J.D., “Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs”, Walter, C., Ko, E., Paar, C., (Editors), Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, Volume 2779, pp. 334-350, Springer Berlin Heidelberg, 2003