Mehran University Research Journal Of Engineering &
Technology (HEC Recognized In Category "X")
Publishing Since 1982.

For Authors
For Readers
Article Information  
Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA

Keywords: Advance Encryption Standard, BRAM, Field Programmable Gate Array, T-Box/T-1-Box

Mehran University Research Journal of Engineering & Technology

Volume 34 ,  Issue 4

Dur-e-Shahwar  Kundi , Arshad  Aziz ,    ,

1. Daemen, J., and Rijmen, V., “AES Proposal: The Rijndael Block Cipher”, pp. 1-45, 1999
2. FIPS-197, “Advanced Encryption Standard”, National Institute of Standards and Technology, 2001
3. Xilinx, “7 Series FPGAs Overview v1.15”, Technical Report, 2014
4. Aziz, A., and Ikram, N., “An Efficient FPGA Based Sequential Implementation of Advanced Encryption Standard”, ITI 3 rd International Conference on Information and Communications Technology, pp. 875-882, Cairo, Egypt, 2005
5. Fischer, V., and Drutarovsky, M., “Two Methods of Rijndael Implementation in reconfigurable hardware”, Proceedings of 3 rd International Workshop on Cryptographic Hardware and Embedded Systems, pp. 77-92, Springer-Verlag, 2001
6. Standaert, F.X., Rouvroy, G., Quisquater, J.J., and Legat, J.D., "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs", Cryptographic Hardware and Embedded Systems Volume 2779, Lecture Notes in Computer Science, pp. 334-350, Springer Berlin Heidelberg, 2003
7. Kundi, D.S., Zaka, S., and Aziz, A., "A Compact AES Encryption Core on Xilinx FPGA", International Conference on Computer, Control and Communication, pp. 1-4, Karachi, Pakistan, 2009
8. Zambreno, J., Nguyen, D., and Choudhary, A., "Exploring Area/Delay Tradeoffs in an AES FPGA Implementation", Proceedings of 14th Annual International Conference on Field-Programmable Logic and Applications, Lecture Notes in Computer Science, Volume 3203, pp. 575-585, Springer, 2004
9. McLoone, M., and McCanny, J., "High Performance Single-Chip FPGA Rijndael Algorithm implementations", Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, pp. 65-76, Springer Verlag, 2001.
10. Wang, J.F., Chang, S.W., and Lin, P.C., "A Novel Round Function Architecture for AES Encryption/Decryption Utilizing Look-Up Table", IEEE 37th Annual International Carnahan Conference on Security Technology, pp. 132-136, Taipei, Taiwan, ROC, 2003
11. Shastry, P., Somani, N., Gadre, A., Vispute, B., and Sutaone, M., "Rolled Architecture Based Implementation of AES Using T-Box", IEEE 55th International Midwest Symposium on Circuits and Systems, pp. 626-630, Boise, Idaho, 2012.
12. Morioka, S., and Satoh, A., "A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture", Proceedings of IEEE International Conference on Computer Design, pp. 98-103, Freiburg, Germany, 2002
13. Xilinx, "7 Series FPGAs Memory Resources User Guide v1.10", Technical Report, 2014. support/documentation/user_guides/ ug473_7Series_Memory_Resources.pdf.
14. Bulens, P., Standaert, F.X., Quisquater, J.J., Pellegrin, P., and Rouvroy, G., "Implementation of the AES-128 on Virtex-5 FPGAs", Progress in Cryptology AFRICACRYPT, Lecture Notes in Computer Science, Volume 5023, pp. 16-26, Springer Berlin Heidelberg, 2008.
15. Drimer, S., Guneysu, T., and Paar, C., "DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs", ACM Transactions on Reconfigurable Technology System, Volume 3, No. 1, pp. 3-27, 2010.
16. Aziz, A., and Ikram, N., "A Look-Up-Table Implementation of AES", International Conference on High Performance Computing, Networking and Communication Systems, pp. 187-191, Orlando, Florida, USA, 2007
17. McLoone, M., and McCanny, J.V., "Rijndael FPGA Implementation Utilizing Look-Up Tables", IEEE Workshop on Signal Processing Systems, pp. 349-360, Antwerp, Belgium, 2001
18. Yoo, S.M., Kotturi, D., Pan, D.W., and Blizzard, J., "An AES Crypto Chip using a Highspeed Parallel Pipelined Architecture", Journal of Microprocessors and Microsystems, Volume 29, pp. 317-326, 2005
19. Ali, L., Aris, I., Hossain, F.S., and Roy, N., "Design of an Ultra-High Speed AES Processor for Next Generation IT Security", Journal of Computers & Electrical Engineering, Volume 37, pp. 1160-1170, 2011.
20. Xilinx, "7 Series FPGAs Clocking Resources User Guide v1.9", Technical Report, 2014. support/documentation/user_guides/ ug472_7Series_Clocking.pdf
21. Rouvroy, G., Standaert, F.X., Quisquater, J.J., and Legat, J., "Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications", International Conference on Information Technology: Coding and Computing, Volume 2, pp. 583-587, Las Vegas, Nevada, 2004