Mehran University Research Journal Of Engineering &
Technology (HEC Recognized In Category "X")
Publishing Since 1982.

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Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim

Keywords: Depth Estimation, Shape From Focus, Hardware Description Language Coder, Field Programmable Gate Arrays.

Mehran University Research Journal of Engineering & Technology

Volume 35 ,  Issue 3



In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.