In this paper single-bit SDM (Sigma Delta Modulation) based TFF (Ternary FIR Filter) with balanced ternary coefficients (i.e. -1/0/+1) has been mapped on small commercially available FPGAs (Field Programmable Gate Arrays). Filter coefficients were obtained using second order sigma delta modulator. The filter structure is based on a hierarchical adder tree that can easily be pipelined for high performance purpose. Filter structure was coded in VHDL (Very High Speed Integrated Circuit Hardware Description Language) and simulated in Quartus-II software. The filter exhibits low I/O (Input Output) and core area usage and high performance-achieving clock speeds close to 200MHz on a low-cost FPGA and over 500MHz on a latest FPGA commercially available device. This single-bit ternary filter is intended to support video and audio processing applications in mobile communication systems.