This work presents an area efficient S-Box technique for implementation of SubByte transform in AES (Advanced Encryption Standard) on Xilinx FPGA (Field Programmable Gate Array). The proposed method optimizes the SubByte transform, allowing eight S-Box to be accommodated in a single embedded BRAM (Block Random Access Memory). The implementation of SubBytes transformation for AES-128 has been done by using two BRAMs only. Those technique will contribute to S-Box implementation of AES, and ultimately impact a vast range of applications of cryptography. The maximum frequency achieved for this design is 155.198 MHz for Spartan-3 and 206.186 MHz for the Virtex-II Pro. Similarly for latest FPGA family Spartan-6 our design has a maximum frequency of 367.241MHz