This paper presents a logically grouped reduced-set implementation of SHA-3 (Secure Hash Algorithm- 3) on Xilinx FPGA (Field Programmable Gate Arrays). In this work, seven computing equations of SHA-3 were logically grouped and reduced down to three set of equations only. These reduced set of equations were then resourcefully realized by using FPGA primitive level programming approach in order to achieve best hardware efficiency. All logical functions were mapped by using LUTs (Look-UpTables) primitives and Fast Carry Chain logic, so that maximum logic may confined within single Slice. Since routing within Slices is local and is very fast as compare to global routing outside the Slices. Therefore, our optimization in term of Slices and vertical routing results in significant area reduction with high frequency. The proposed architecture on Virtex-7 FPGA utilizes only 800 Slices with highest throughput of 16.37 Gbps and offers most efficient TPA (Through Per Area) of 20.46.